The present invention relates to the dense packaging of electronic circuitry and specifically to the stacking of ball grid array (BGA) format integrated circuit packages. The invention is also suitable for the stacking of fine ball grid array (FBGA) integrated circuit packages, micro-ball grid array packages and for bump-bonded bare die to form stackable layers which can be combined to form multi-layer electronic modules.
The electronics industry continues to seek smaller, denser electronic packaging. An important advance in this regard has been the use of three-dimensional packaging techniques using stacked bare or packaged integrated circuit die.
Most of the background art disclosures describe methods of stacking multiple unpackaged IC chips. Oguchi et al., U.S. Pat. No. 5,332,922, Miyano et al., U.S. Pat. No. 5,440,171, and Choi et al., U.S. Pat. No. 5,677,569, disclose methods of stacking IC chips within a single package. Jeong et al., U.S. Pat. No. 5,744,827 discloses a new type of custom chip packaging which permits stacking, but which does not allow the use of off-the-shelf packaged IC's. Burns, U.S. Pat. No. 5,484,959 shows a method of stacking TSOP packages which requires multiple leadframes attached above and below each TSOP and a system of vertical bus-bar interconnections, but which does not conveniently allow an expansion of the number of vertically interconnecting leads.
The assignee of this application, Irvine Sensors Corporation, has been a leader in developing high-density packaging of IC chips, for use in focal plane modules and for use in a variety of computer functions such as electronic memory. Examples of Irvine Sensors Corp.'s high-density electronic packaging are disclosed in U.S. Pat. No. 4,672,737, to Carson, et al.; U.S. Pat. No. 5,551,629, to Carson et al.; U.S. Pat. No. 5,688,721, to Johnson; U.S. Pat. No. 5,347,428 to Carson, et al.; and U.S. Pat. No. 6,028,352 to Eide, all of which are fully incorporated herein.
The present invention relates to the stacking of layers containing integrated circuit chips (ICs), thereby obtaining high-density electronic circuitry. In general, the goal of the present invention is to combine high circuit density with reasonable cost. A unique aspect of this invention is that it provides a low cost method of stacking commercially available IC's in BGA packages while allowing the independent routing of several non-common UO (input/output) signals from upper-level layers to lower layers or to the bottom of the stack. Cost reduction is accomplished by utilizing relatively low cost interposer boards as appropriate to reroute leads to an access plane and by the ability to stack pre-packaged and pre-tested off-the-shelf BGA packages.
None of the background art addresses the need for compact, dense microelectronic stacks that take advantage of the high speed and small outline of a BGA package that are low cost and highly reliable and incorporate known good die (KGD), each aspect of which the instant invention addresses.